1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a data writing circuit in a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having an operation mode to simultaneously write the same data to more memory cells than a normal writing operation.
2. Description of the Background Art
In recent years, more semiconductor memories have been utilized in the field of graphics. The semiconductor memory utilized in the field is required of a so-called "block writing" function. For example, some SGRAM (Synchronous Graphic Random Access Memories) have such "block writing" operation mode as a function advantageous for high speed operation such as clearing the picture plane.
Meanwhile, a DRAM core in an embedded DRAM/logic circuit chip including both a DRAM (Dynamic Random Access Memory) and a logic circuit for processing graphic data is required of the "block writing" function.
The block writing function corresponds to the function of simultaneously writing the same data to more memory cells than a normal writing operation in terms of operations of the DRAM.
FIG. 16 is a schematic block diagram of the configuration of a semiconductor memory device 5000 having a conventional block writing function.
Semiconductor memory device 5000 includes four memory cell array mats #M0 to #M3. Each memory cell array mat includes memory cells arranged in a matrix of rows and columns. A row decoder 5110 and a column decoder 5200 are provided corresponding to each of the memory cell array mats. Row decoder 5110 responds to an externally applied address signal to select a corresponding row (word line), and column decoder 5200 responds to an externally applied address signal to select a corresponding column.
A bit line pair BL, /BL (not shown) is provided corresponding to each of the memory cell columns, and in a writing column decoder 5200 provides writing data to bit line pair BL, /BL corresponding to a selected column.
FIG. 17 is a schematic block diagram for illustrating further in detail the configuration of column decoder 5200 shown in FIG. 16.
A column address buffer 5202 generates internal column address signals CA0, /CA0 to CAm, and /CAm based on an externally applied column address signal. A column predecoder 5204 receives internal column address signals CA0, /CA0 to CAm, and /CAm and outputs a predecoded signal. Column decoder 5200 includes column selecting signal generation circuits 5206a to 5206d for selecting a corresponding memory cell based on the predecoded internal column address signal received from column predecoder 5204.
FIG. 17 shows the configuration of column selecting signal generation circuits 5206a to 5206d (which corresponds to the region within the ellipse shown in FIG. 16) for memory cell array mat #M3 shown in FIG. 16.
Referring to FIGS. 16 and 17, memory cell array mat #M3 is divided into four sub-blocks, sub-blocks 0 to sub-block 3, similarly to other memory cell array mats #M0 to #M2. Each sub-block equally includes one fourth the columns included in memory cell array mat #M3.
Column selecting signal generation circuits 5206a to 5206d are provided corresponding to sub-blocks 0 to 3, respectively.
Sub-blocks 0 to 3 each include one redundant column.
Column selecting signal generation circuit 5206a includes an address comparison circuit 5230 which receives a predecoded internal column address signal and activates a spare active signal SPA for activating the redundant memory cell column if a prestored defective address matches the predecoded internal column address signal, an inverter 5228 which receives spare active signal SPA and outputs the inverse thereof, and an AND circuit 5210 which receives the predecoded internal column address signal, the output of inverter 5228, an externally applied address signal, and a sub-block activation signal SBA0 attaining an active state ("H" level) when sub-block 0 is selected, and outputs a column selecting signal CSL1 based on the logical product thereof.
In response to column selecting signal CSL1, a memory cell column in corresponding sub-block 0 is selected.
A column selecting signal CSL2 to select the second memory cell column in sub-block 0 is output from an AND circuit 5220 for operating the logical product of signal SBA0, the predecoded internal column address signal, and the output of inverter 5228.
An AND circuit identical to AND circuit 5210 is provided corresponding to a column selecting signal CSLi (i=1 to n, n: natural number) corresponding to each memory cell column included in sub-block 0. For example, a column selecting signal CSLn corresponding to the n-th memory cell column included in sub-block 0 is output from an AND circuit 5224 which receives the predecoded internal column address signal and the output of inverter 5228.
Column selecting signal generation circuit 4206a further includes an AND circuit 5226 which receives spare active signal SPA and sub-block activation signal SBA0 and outputs a signal SCSL to select a redundant memory cell column.
More specifically, if a predecoded internal column address signal matches a defective address stored in a non-volatile manner in address comparison circuit 5230, spare active signal SPA attains an active state ("H" level). A signal output from inverter 5228 attains an "L" level accordingly, and therefore column selecting signals CSL1 to CSLn output from AND circuits 5210 to 5224 are all brought into an inactive state ("L" level).
Meanwhile, if signal SPA is in an active state and sub-block activation signal SBA0 attains an active state ("H" level), signal SCSL to select a redundant memory cell column attains an active state ("H" level).
If the predecoded internal column address signal does not match the defective address stored in address comparison circuit 5230, spare active signal SPA is in an inactive state ("L" level). Thus, a signal output from inverter 5228 attains an "H" level. Depending upon the value of the predecoded internal column address signal, column selecting signal CSLi (i=1 to n) output from one of AND circuits 5210 to 5224 each provided corresponding to a memory cell column is activated, and a corresponding memory cell column is selected as a result.
As described above, if a memory cell column including a defective memory cell is included in sub-block 0, by allowing address comparison circuit 5230 to previously store the defective address, the memory cell column corresponding to the defective address is replaced with the redundant memory cell column.
Column selecting signal generation circuits 5206b to 5206d provided corresponding to sub-blocks 1 to 3, respectively also include the same configuration.
Herein, sub-blocks 1 to 3 are selected as sub-block activation signals SBA1 to SBA3 attain an active state, respectively, in response to an externally applied address signal, so that a memory cell column in a sub-block is selected.
In semiconductor memory device 5000 as shown in FIGS. 16 and 17, one column selecting signal CSLi is activated in a selected sub-block during a normal reading/writing, and only one column is selected. None of column selecting signals is activated for the non-selected sub-blocks.
If, for example, among the four sub-blocks, two sub-blocks are activated, and the other two sub-blocks are in an inactive state, two memory cell columns are simultaneously selected in one memory cell array mat.
Meanwhile, in the above-described block writing mode, the four sub-blocks are all activated, in other words all the sub-block activation signals SBL0 to SBL3 attain an "H" level, and the four memory cell columns are simultaneously selected in one memory cell array mat.
By such operations, during the block writing operation, data may be simultaneously written to memory cells as twice as the number of memory cells written in a normal writing.
In the above-described SGRAM, if the bus width (the number of data bits exchanged at a time) of a data bus exchanging data with the outside may be increased, the device may be more advantageously used for high speed data transfer.
Furthermore, in a chip including both DRAMs and logic circuits, which has attracted much attention in recent years, by securing a large internal data bus width between a DRAM and a logic, the data transfer rate between the DRAM and the logic can be increased.
If the block writing operation mode is implemented by the method as described in conjunction with FIG. 17, however, it is difficult to increase the bus width for exchanging data with the outside (the internal bus width in the chip including both DRAMs and logic circuits) in the DRAM.
More specifically, the "large bus width" allows much data to be simultaneously read out/written from/to one memory cell array mat. To this end, column selecting signals as many as possible must be activated at a time in one memory cell array mat.
In the configuration shown in FIG. 17, however, the number of column selecting signals which can be activated at a time in one memory cell array mat (the number of memory cell columns which can be selected at a time) is defined by the number of sub-blocks formed by dividing the memory cell array mat.
As in the foregoing, one sub-block is a unit for replacement of a redundant memory cell column. If the number of sub-blocks is arbitrarily increased, the ratio of redundant memory cell columns to normal memory cell columns included in one memory cell array mat increases. As a result, there exists a limitation in increasing the number of sub-blocks while restraining the memory cell array area from being increased.